1. Field of the Invention
The present invention relates to a memory and a method of reading data out of the memory.
2. Description of the Related Art
Compared with a DRAM (Dynamic Random Access Memory), a VRAM (Video RAM) is provided with, in addition to a regular random access circuit a sequential access circuit whose chip area is relatively large, and the number of input/output terminals in the VRAM is about twice that of ordinary DRAM. As a result, the price of VRAM is also about twice that of ordinary DRAM.
Synchronous DRAM, as shown in FIG. 4, has been developed to cope with the ever higher speeds of system clocks in microprocessors.
A synchronous DRAM performs latching of commands and input/output of data in synchronization with the rising edge of a clock pulse CLK which is externally provided. The time required by synchronous DRAM to access the first data is approximately the same as that of asynchronous type DRAM, but it can read out second data and subsequent data in clock units at high speed. It is also provided with a memory cell array 10 of bank 0 and a memory cell array 20 of bank 1, and by reading, for instance, every four words out of the memory cell array 10 and the memory cell array 20 alternately, the precharge time can be hidden and access can be performed continuously even when the row addresses are different. Synchronous DRAM has less chip area than VRAM and is, therefore, cheaper.
It follows that there is demand for such synchronous DRAM to be used in typical VRAM applications.
However, in case that, while data are continuously read out of the memory cell array 10 and the data are being converted to video signals, other data are also read out of another address in the memory cell array 10 by an image processing application program to overwrite the contents of the memory cell array 10 in correspondence to the value of that other data, data cannot be read alternately out of the memory cell array 10 and the memory cell array 20. Consequently, as shown in FIG. 5, continuous data access cannot be performed, generating wasted time.
Specific explanation is given as to how this problem occurs in reference to FIG. 5. FIG. 5 shows an operation performed in accordance with the JEDEC standards. As shown in FIG. 5, the Burst Length is 4 and the CAS Latency is 2. Bit lines of the memory cell array 10 is precharged before t0. In the following explanation, the operation described in (t0), for instance, refers to a sequence of operations starting at the time t0.
(t0) A control circuit 31 causes row address buffer register (row buffer) 11 to hold the address AD as RA01. This row address RA01 is decoded by a row decoder 12, which selects one row in the memory cell array 10 and the contents of selected row are then read out on a bit line. The data on the bit line are then amplified by a sense amplifier 13.
(t2) The control circuit 31 causes a column address counter (column buffer) 15 to hold the address AD as CA01. This column address CA01 is decoded by a column decoder 16 and data D00 on the bit line, which correspond to the output from the column decoder 16, are provided to an input/output circuit 30 via a column switching circuit 14. This data D00, is then held at a flip-flop in the input/output circuit 30 for output.
(t4) At the time t4, the data D00 output from the are read from the outside and the control circuit 31 provides a clock to the column address counter 15 to increase the column address. Data D01 on the bit line, which correspond to this column address, are provided to the input/output circuit 30 via the column switching circuit 14. This data D01 is then held at the flip-flop in the input/output circuit 30 for output.
Subsequently, an operation identical to that performed at time t4 is repeated until time t7, and from t4 through t7, continuous 4-word data D00 to D03 are output from the input/output circuit 30.
(t6) In preparation for the next access, bit lines in the memory cell 10 is precharged. As stipulated in the JEDEC standards, during this precharge, the contents of the row address buffer 11 and the column address buffer 16 and the contents of the flip-flop in the input/output circuit 30 are all cleared. However, since one cycle or the clock CLK is extremely short, 10 ns, for instance, the output of data D03 at the time t7 is assured by the propagation delay from the time t6, at which the external signal is received, to the time when said clear is executed.
(t9 to t13) In a manner similar to that in which the operation from tO through t4 is performed, continuous 4-word data DX0 to DX3 out of one row selected by another word line in the memory cell array 10 of the same bank 0 are output from the input/output circuit 30 at t8 to t12.
As a result, the 5 clock cycles from t8 through t12 become wasted time.